The present invention relates, in general, to the field of integrated circuit (“IC”) devices incorporating memory arrays. More particularly, the present invention relates to an integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section.
Many types of DRAM based devices, or integrated circuits including embedded memory arrays, are currently available including extended data out (“EDO”), synchronous DRAM (“SDRAM”), double data rate (“DDR”) DRAM and the like. Regardless of configuration, the primary purpose of the DRAM is to store data. Functionally, data may be written to the memory, read from it or periodically refreshed to maintain the integrity of the stored data. In current high density designs, each DRAM memory cell comprises a single pass transistor coupled to an associated capacitor that may be charged to store a value representative of either a logic level “1” or “0”. Data stored in these memory cells may be read out and written to them through columns of sense amplifiers coupled to complementary bit lines interconnecting rows of these cells.
Memory architectures are generally designed to incorporate a predetermined number of gate delays in order to get the column information from the address generation portion of the IC to the memory sub-arrays (and/or banks). This delay is uniform for all of the sub-arrays. A certain number of gate delays is also employed to get critical clock and control information from the clock/control generation section to the sub-arrays and to the input/output (“I/O”) section of the device. Again, this delay is relatively uniform across the entire architecture. Finally, the “read” data, coming from the memory sub-arrays and directed to the I/O section of the chip also has a certain amount of delay associated with it that is also substantially constant across the entire architecture. In practice, a simple formula can be developed describing the gate counts and delays for the column address, how these integrate with the clock/control information and how the data generated from these addresses and clocks is eventually output at the I/O section, which is substantially identical for every sub-array in the architecture, regardless of its physical location on the chip.
However, with extremely large chips, two extreme cases result. First, memory sub-arrays near the address/control section receive that information most quickly while the “read” data has a long delay before reaching the I/O section. Secondly, sub-arrays more remote from the address/control section receive those signals relatively slowly while the “read” data is only a short delay from the device I/O section.
Given the extremely tight timing requirements for modern memories, minimizing the skew between these two cases is critical for high speed operation. This is especially true for double data rate synchronous dynamic random access memory (“DDR SDRAM”) devices wherein all data must be read simultaneously at the I/O section, regardless of from where in the architecture it originated.